With LCD monitors are gradually entering the TV market, higher resolution, larger size and deeper color depth panel requirements are increasing DS1642-150 Price . All these demands require higher data transfer rates DS1642-150 Price . However, a reliable data link, in the high transmission rate should be no compromise DS1642-150 Price .
therefore need a very robust and reliable interface solution that can work through fewer but higher frequency data lines for data transmission. With the traditional multi-branch structure than is called PPDS (Point to Point Differential Signaling) for point to point interface architecture can ensure the use of fewer data lines from a T-con (Tx) to CD (Rx) and reliable data transmission. ST Microelectronics (ST) the company's design team is currently being developed PPDS corresponding chip that only can be achieved using a pair of channel FHD/120Hz reliable data transfer applications.
1. To the benefits of PCB design PPDS and other interfaces using different protocols. PPDS protocol as a variety of information transmitted via the data cable, so no need to configure the function of pins, and no additional wires.
Application PPDS can get benefits. Since the data output pin and the other to reduce the number of control lines, T-con size smaller. As each CD has an internal termination resistor inside, so no longer need a separate data line termination resistor. Because a small number of data lines, gamma reference voltage is low, so you can design a very thin PCB.
In addition, the data transmission characteristics are also better because snacked clock connection with the PCD design does not overlap, and need not have holes, thus greatly reducing the electromagnetic interference (EMI). Another advantage is that, as to be mentioned later, through the use of recycled DAC, chip size has become smaller.
2. LVDS10 when the input signal, the T-con within the lookup table can be driven on-chip 12-bit linear DAC Digital generate 12-bit digital code.
switch to 12-bit digital gamma can use the driver chip 12-bit DAC in 10-bit color.
3.PPDS digital gamma-gamma system in Figure 3 for digital and traditional systems were compared. Traditional systems installed in the driver IC through the R-ladder can be regenerated 8-bit digital data.
in the digital gamma system, the driver IC implemented by the lookup table information for the existing 10-bit gamma, find the table that is driven by the chip 10-bit linear DAC in 8-bit color input based on regeneration from The.
4.PPDS protocol Figure 4 shows the line through the data sent to the protocol. Such as the pixel inversion, charge sharing time, line delay compensation, pre-charge setting and the black frame (BlackFrame) and other information are inserted into each data line of data previously sent.
5. Horizontal line delay compensation (HLDC) when the panel is large, due to the increase of the gate line load often cause signal delay, and thus shorten the charging time. To prevent this problem, connect both ends is connected to a gate driver chip, however, doing so will not only increase costs, and can only recover 50% of the charging time.
PPDS can divide it up into 6-8 out of time to control the output of each chip or chips, so as to effectively protect the gate signal delay caused by the charging time of loss. In this case no need to use a door connecting both ends of the driver chips. The output of the source driver IC also be controlled to the same gate signal delay, so that the charging time of the loss to a minimum.
6. To shift functions can be carried out in each line to the offset test, in order to select the best clock / data delay, and to keep each before sending configuration or data.
DAC for LCD Driver IC
terms of LCD driver chips, DAC method can be divided into R-DAC and C-DAC. R-DAC is the series resistance as shown below (Figure 5), used to select digital rate consistent with output voltage. For 10-bit R-DAC, there is a 2X1024 trapezoidal (R-ladder) block row.
terms of R-DAC, R-ladder size becomes larger, depending on the number of grayscale bits. 10-bit R-DAC's R-ladder size is four times bigger than the 8-bit. In order to solve the problem size increases, you can design a new method of interpolation. Cycle through repeated sampling and DAC to output data to keep: 2 times by switching capacity to achieve.
benefits of recycling DAC
1. Chip size small cycles DAC's greatest advantage is not with the gray-bit chip size increases. This was due to cyclic DAC stack architecture that consists of two DAC-down, one each composition. Capacitor DAC with 2 each, no matter how much the number of bits, they can reduce the chip size.
2. Low-power driver IC most of the power loss in the buffer amplifier above. DAC in the loop buffer amplifier designed to be simple, it can significantly reduce power consumption.
3. Lower chip temperature as low power consumption, so the chip temperature is very low. The temperature under the same conditions on the comparison showed that the cyclic DAC in FHD/60Hz the temperature below 10 ℃. Due to lower temperature, eliminating the need to use the top of the ground plate and thermal pad, which effectively improve the cost-effective.
4. Low output voltage error to reduce the chip size, R-DAC design using interpolation. Shown in Figure 7, 10-bit R-DAC to form an 8-bit R-ladder, switching the extra two, the final output 10. Interpolator resistance error and the error will affect the AVO (between the driver chip output voltage deviation) and the DVO (Driver internal output voltage deviation), but the DAC in the loop case, there is only capacitive errors. Since the error is much smaller than the resistive capacitive error and therefore have more accurate output characteristics.
5. Less number of gamma reference voltage due to circular DAC output voltage by switching decision, and the number of gamma reference voltage is 6, this number is much smaller than the R-DAC, and has nothing to do with the number of grayscale bits . The 10-bit R-DAC requires a reference voltage of 18-22, GS will also be required to increase more. Because a small number of reference voltage, PCB size can do less. The smaller number of cable and connector pins will also help reduce material costs.
6. Each channel has two DAC. When the first DAC conversion is complete, the second DAC is driven, and the beginning of the output stage of the data remains unchanged after the conversion. And as shown in Figure 7, R-DAC in the R-ladder, decoder and amplifier are preparing for a treatment of the rising / falling edge delay.
Many engineers believe that the error or the reliability of the capacitor worse than resistance. However, the production of wafers with a 1000 chip used to drive the R-DAC and DAC cycle reliability and matching measurements and analysis show that the resistance of polyethylene capacitor is better than polyethylene, the former is more likely to get more accurate output .
PPDS is designed for thin PCB, because the T-con from the connection to the small number of driver chips. PPDS can use to send a large number of driver chips protocol control information to the data lines. In addition, there HLDC and to shift functions, which help ensure pixel charging time, respectively, and send / receive secure data.
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